1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage apparatus for use in a flash memory or the like and a manufacturing method therefore. More particularly, the present invention relates to a non-volatile semiconductor storage apparatus for improvement of a memory cell capacity and a manufacturing method therefore.
2. Description of the Related Art
Conventionally, a variety of non-volatile semiconductor storage apparatuses are such that one memory cell transistor is provided at one unit cell, and one memory cell transistor and one select transistor are provided at one unit cell.
FIG. 1A to FIG. 1C are sectional views showing a conventional method of manufacturing a non-volatile semiconductor storage apparatus in which one memory cell transistor and one select transistor are provided at one unit cell in order of steps. In addition, FIG. 2 is a layout showing a non-volatile semiconductor storage apparatus manufactured by the methods shown in FIG. 1A to FIG. 1C. The sectional views shown in FIG. 1A to FIG. 1C show sectional views, each of which indicates a position along line D—D in FIG. 2.
In this conventional manufacturing method, a plurality of field insulation films 104 for element separation are first formed in an island shape on a surface of a silicon substrate 101. Next, as shown in FIG. 1A, a surface of the silicon substrate 101 is thermally oxidized, whereby a tunnel gate oxide film 105 is formed in a region that is to be an active region. Further, a polysilicon film 106 is stacked on the tunnel gate oxide film 105. Next, a portion that is to be a gate of a memory cell transistor of the polysilicon film 106 is etched in a slit shape.
Next, as shown in FIG. 1A, an oxide film, a nitride film, and an oxide film are stacked in order on the polysilicon film 106, thereby forming an ONO film 115. Thereafter, a polysilicon film 116 is fully stacked. Further, a photo-resist film 117 is formed on the polysilicon film 116, and this photo-resist film 117 is patterned in the shape of the gate electrode of each transistor.
Then, as shown in FIG. 1B, the photo-resist film 117 is defined as a mask, and the polysilicon film 116, ONO film 115, polysilicon film 106, and tunnel oxide film 105 are sequentially removed in order by etching through self-alignment. Next, N-type impurities, for example, arsenic (As) is ion-implanted into the silicon substrate 101, and an N+ diffusion film 109 is formed as an active region. Of the N+ diffusion layer 109, an N+ diffusion layer 109a in FIG. 1B is obtained as a source diffusion layer, and an N+ diffusion layer 109b in FIG. 1B is obtained as a drain diffusion layer. Thereafter, an oxide film is fully stacked, and the stacked film is etched back, thereby forming a side wall 118. Next, a transistor with an LDD structure is formed by carrying out ion-implantation with high density. In two transistors sandwiching the N+ diffusion layer 109a, the polysilicon films 106 and 116 sandwiching the ONO film 115 are connected to each other.
Then, as shown in FIG. 1C, an interlayer insulation film 119 is fully stacked; a contact hole 120 reaching the N+diffusion layer 109b, which is a drain, is formed in the interlayer insulation film 119; a wiring layer 121 is embedded in this contact hole 120; and further, a wiring layer 122 commonly connecting the wiring layer 121 in a transverse direction is formed as a bit line.
FIG. 3A to FIG. 3D are sectional views showing a conventional method of manufacturing an non-volatile semiconductor storage apparatus in which one memory cell transistor is provided at one unit cell in order of steps. In addition, FIG. 4 is a layout showing a non-volatile semiconductor storage apparatus manufactured by using a method shown in FIG. 3A to FIG. 3D. FIG. 3A to FIG. 3D show sectional views, each of which indicates a position taken along line E—E in FIG. 4.
In this conventional manufacturing method, a plurality of field insulation films 154 for element separation extending in a transverse direction is linearly formed on a surface of a silicon substrate 151. Next, as shown in FIG. 3A, a surface of the silicon substrate 151 is thermally oxidized, whereby a tunnel gate oxide film 155 is formed in a region that is to be an active region. Further, a polysilicon film 156 is stacked on the tunnel gate oxide film 155, and the polysilicon film 156 on a linearly formed field insulation film 154 is removed in a slit shape by means of etching. Next, an oxide film, a nitride film, and an oxide film are stacked on the polysilicon film 156, thereby forming an ONO film 165. Thereafter, a polysilicon film 166 is fully stacked. Further, a photo-resist film 167 is formed on the polysilicon film 166, and this photo-resist film 167 is patterned in the shape of the gate electrode of each memory cell transistor.
Then, as shown in FIG. 3B, the photo-resist film 167 is defined as a mask, the polysilicon film 166, the ONO film 165 and polysilicon film 156, and the tunnel gate oxide film 155 are sequentially removed by etching through self-alignment. Next, N-type impurities, for example, arsenic (As) is ion-implanted in the silicon substrate 151, whereby the N+ diffusion layer 159 is formed as an active region. Of the N+ diffusion layer 159, an N+ diffusion layer 159a in FIG. 3B is obtained as a source diffusion layer, and an N+ diffusion layer 159b in FIG. 3B is obtained as a drain diffusion layer. Thereafter, an oxide film is fully stacked, and the stacked film is etched back, thereby forming a side wall 168. Next, a transistor with an LDD structure is formed by carrying out ion-implantation with high density.
Next, as shown in FIG. 3C, a silicon oxide film 161 is fully stacked.
Next, as shown in FIG. 3D, an opening reaching the N+ diffusion layer 159 is formed in the silicon oxide film 161 on the drain and source regions, and then, a polysilicon film 163 is fully stacked. Then, the polysilicon film 163 is connected by a polysilicon film 163b in parallel to a word line on the drain region so as to dispose the polysilicon stay 163a at the individual openings on the drain region, and is patterned so as to be a common source line. Thereafter, an interlayer insulation film 169 is fully laminated; a contact hole 170 reaching the polysilicon stay 163 is formed; a wiring layer 171 is embedded in the contact hole 170, and further, a wiring layer 172 commonly connecting the wiring layer 171 in a transverse direction is formed as a bit line.
In the non-volatile semiconductor storage apparatus manufactured by these methods, while an element becomes finer and a voltage is lowered, a capacity between a control gate and a floating gate of a memory cell transistor is so small that a sufficient coupling capacity cannot be obtained. Thus, a high voltage is required for that operation, making it impossible to cope with a recent requirement for a reduced operating voltage and leading to an increase in a step for increasing an area for a pressure rise circuit for generating an operating voltage and an increase in a step for generating a pressure rise circuit. In addition, a gate oxide film and an ONO film are thin-filmed, thereby making it possible to improve a coupling capacity. However, in this method, the reliability of a memory cell may be lost due to generation of a leak current or the like, and thus, there is a restriction on thin filming.
On the other hand, there is proposed an AND-type semiconductor non-volatile memory in which a pair of source and drain regions and two channel regions are provided in one unit cell; a select gate, a floating gate and a control gate are provided in order from the lower part per one of the two channel regions; and the floating gate is used as a gate in the other channel region (Japanese Patent Application Laid-open No. Hei 9-129759). FIG. 5 is a sectional view showing a conventional semiconductor non-volatile memory described in Japanese Patent Application Laid-open No. Hei 9-129759.
In the conventional semiconductor non-volatile memory proposed in this publication, as shown in FIG. 5, a source region 202 and a drain region 203 are formed at a surface of a semiconductor substrate 201; a select gate 204 is formed via a gate insulation film 211 at a position eccentric at the source region 202 side on a channel region sandwiched by the source region 202 and the drain region 203; and a floating gate 205 is formed via a gate insulation film 212 at a position eccentric at the drain region 203 side. This floating gate 205 extends upwardly of the select gate 204 via an insulation film 214. These are covered with an insulation film 213, and a control gate 206 is formed on this insulation film 213.
According to the thus configured conventional semiconductor non-volatile memory, an area in which the control gate 206 is superimposed on the floating gate 205 is greater than an area in which the floating gate 205 is superimposed on the select gate 204, thus making it possible to increase a coupling capacity without increasing an area for a unit cell. In addition, one drain contact is shared by 128 unit cells, for example, thus making it possible to reduce the cell area.
However, in a conventional semiconductor non-volatile memory shown in FIG. 5, in order to form the floating gate 205 and the select gate 204, when a polysilicon film is patterned in batch, a drain side semiconductor substrate 201 is also etched. Therefore, a fault may occur in this region, and a malfunction may occur due to generation of a leak current in a diffusion layer that configures the drain region 203. On the other hand, in the case where the floating gate 205 and the select gate 204 are formed in another step in order to prevent this fault or malfunction, a pattern shift or non-uniformity occurs, and the characteristics becomes easily non-uniform. Thus, it is improper to ensure fining. In addition, the channel length of a transistor having the gate oxide film 212 and a channel length of a transistor having a gate oxide film 211 are also easily made non-uniform. Thus, there is a problem that the characteristics are easily made non-uniform. In addition, in an AND-type semiconductor non-volatile memory, the drain and source of each of a number of transistors are formed in a common diffusion layer, and are connected to a wiring layer at an end of the diffusion layer. Thus, there is a problem that a parasitic resistance in the source and drain is large.